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Device Simulation (TCAD Lab)

The semiconductor device simulation lab was established in the year 2009. It’s in the ground floor of IT department, SSN College of Engineering. Dr Srinivasan, IT, is heading this lab. Dr Nagarajan, EEE, and Dr Durga, ECE are the other faculty members using this lab.

 

The lab has produced 13 Ph.D. Research scholars, from 2009 to till date (May 2025). All of them received their PhD degree from Anna University, Chennai. Currently three scholars are pursuing their Ph.D. Most of them pursued their research with stipend. In the past, PG students also used this lab for their final year project. Three government projects have been executed in this lab. The lab has generated 40 journal publications (WoS) since its establishment.

SRF-SSN

NameDuration
Dr. S. Priscilla Scarlet2014 – 2016
Dr. P. Rajendiran2019 – 2020
P. Sasikala2024 – till date (May 2024)

JRF

NameDurationAgency
Dr. Lakshmi2009-12DST
Dr. N. Vinodh Kumar2012-2015DRDO
Dr. R. Ambika2015-2017SSN
Dr. S. Priscilla Scarlet2014-2016SSN
Dr. Nisha Justeena2018-2021SSN
P. Sasikala2021-2023SSN
Indra Chatterjee2021-2023BRNS
Rashmita2023 – till date (May 2024)SSN

Publications from the lab

  1. S Rashmita, R Srinivasan, “Simulation of Ring-FinFET and its performance analysis”, Micro and Nanostructures, Volume 207, 2025, ISSN 2773-0123, https://doi.org/10.1016/j.micrna.2025.208309 (ScienceDirect Link)
  2. Arvind Kumar Singh, Suresh Durai, Srinivasan Raj, and Anbarasu Manivannan, “Impact of Eccentricity on the Performance of Nanotube Phase Change Memory Devices”, Physica Status Solidi (RRL) – Rapid Research Letters, Vol. 19, No. 11, July 2025, Published ONLINE 21st Feb 2025, https://doi.org/10.1002/pssr.202400424
  3. Indira Chatterjee, and R Srinivasan, “Dual doped ring reconfigurable FET and its process variation analysis using random forest algorithm”, Micro and Nanostructures, Vol. 198, Feb 2025, https://doi.org/10.1016/j.micrna.2024.208056
  4. Rajendran P, and Srinivasan R, “Radiation influence on planar reconfigurable field effect transistor low noise amplifier performance”, Physica Scripta, Vol. 99, No. 11, Oct 2024, https://doi.org/10.1088/1402-4896/ad7f9a
  5. G Durga, and R Srinivasan, “Bulk substrate based reconfigurable field-effect transistor and its single event effect performance”, Multiscale and Multidisciplinary Modeling, Experiments and Design, Vol. 7, Aug 2024, pp. 6035–43, https://doi.org/10.1007/s41939-024-00571-8
  6. Sasikala PanneerSelvam, Sirish, TanuShyam Bhattacharjee, Premanand Venkatesh Chandramani, and Srinivasan Raj, “Impact of Process Variation on Leakage and Drive Currents of FED Structures Using Linear Regression and Random Forest Algorithms”, Silicon, Vol. 16, 2024, pp. 995–64, Springer Link
  7. Sasikala PanneerSelvam, Susanta Kumar Pal, Premanand Venkatesh Chandramani, Srinivasan Raj, “Single event performance of FED based SRAMs using numerical simulation”, Microelectronics Reliability, Volume 142, 2023, 114930, ISSN 0026-2714, Elsevier Link
  8. R Srinivasan, “Scalable Hridaya Kolam and Aishwarya Kolam”, Journal of Mathematics and Arts, Vol. 17, 2023, https://doi.org/10.1080/17513472.2023.2185055
  9. G Durga, Susantakumar Pal, and R Srinivasan, “Reconfigurable FET based Tunable Ring Oscillator and its single event effect performance”, Journal of Circuits, Systems and Computers, Vol. 31, No. 18, 2022, World Scientific Link
  10. Suresh Durai, K C Chandinin Devi, Srinivasan Raj, and Anbarasu Manivannan, “Impact of Process Induced Ellipticity on the Reset Process of Cylindrical Phase Change Memory Devices”, Physica Scripta, Vol. 97, No. 12, 2022, IOP Link
  11. L K Pavithra, R Srinivasan and T Sree Sharmila, “Optimum Anamorphic Image Generation Using Image rotation and relative Entropy”, Multimedia Tools and Applications, Springer, 22nd April 2022 (Published Online)
  12. Scarlet, S.P., Vinodhkumar, N. & Srinivasan, R. “Performance enhancement of junctionless silicon nanotube FETs using gate and dielectric engineering”, Journal of Computational Electronics, Vol. 20, Nov 2020, https://doi.org/10.1007/s10825-020-01611-5
  13. Rajendran P, Nagarajan K K, and Srinivasan R, “Investigation of heavy ion strike on FinFET based low noise amplifier”, Semiconductor Science and Technology, Vol. 35, Nov 2020.
  14. Suresh Durai, Srinivasan Raj, and Anbarasu Manivannan, “Impact of Thermal Boundary Resistance on the Performance and Scaling of Phase Change Memory Device”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 39, No. 9, Sep 2020, pp. 1834–1840.
  15. Nisha Justeena, and R Srinivasan, “Reconfigurable FET-Based SRAM and Its Single Event Upset Performance Analysis Using TCAD Simulations”, Microelectronics, Volume 101, July 2020.
  16. Nisha Justeena, and R Srinivasan, “Reconfigurable Silicon Nanotube FET Using Numerical Simulations”, Journal of Computational Electronics, Vol. 19, May 2020, pp. 966–974.
  17. Suresh Durai, Srinivasan Raj, and Anbarasu Manivannan, “Impact of Process-induced Variability on the Performance and Scaling of Ge2Sb2Te5 Phase-Change Memory Device”, Semiconductor Science and Technology, Vol. 35, No. 3, Feb 2020.
  18. Suresh Durai, Srinivasan Raj, and Anbarasu Manivannan, “An extremely fast, energy-efficient RESET process in Ge2 Sb2 Te5 phase change memory device revealed by the choice of electrode materials and interface effects”, Semiconductor Science and Technology, Vol. 35, No. 1, Dec 2019.
  19. Rajendran P, and Srinivasan R, “Single Event Radiation Performance Analysis of Junction and Junctionless FET-based Low Noise Amplifier”, Journal of Computational Electronics, Vol. 18, No. 3, July 2019, pp. 1162–1172.
  20. Rajendran P, and Srinivasan R, “Heavy ion impact on narrow band cascoded low noise amplifier”, Microelectronics Reliability, Vol. 91, Part 1, pp. 31–37, 2018, ISSN 0026-2714.
  21. Scarlet, S.P. and Srinivasan, R., “Optimization of nanometer bulk junctionless Trigate FET using gate and isolation dielectric engineering,” Material Science in Semiconductor Processing, Vol. 84, Mar 2018, pp. 107–114.
  22. R. Ambika, R. Srinivasan, “Sensitivity of Silicon nanotube FETs to structural process parameters”, Journal of Nanoelectronics and Optoelectronics, Vol. 12, 2017 (ASP Publisher).
  23. Priscilla Scarlet, and R Srinivasan, “Nanoscale Junctionless Device Using RingFet Structure on Bulk Silicon Substrate”, International Journal of Electronic Letters, 2017.
  24. Priscilla Scarlet, and R Srinivasan, “Performance Optimisation of Junctionless FET in Nano regime using Segmented Channel – A 3D Numerical Simulation Study”, Superlattices and Microstructures, Vol. 111, 2017.
  25. N. Vinodhkumar, and R. Srinivasan, “SET and SEU performance of Single, Double, Triple and Quadruple-Gate Junctionless FETs Using Numerical Simulations”, Microelectronics Journal, Vol. 67, Sep 2017, pp. 38–42.
  26. R. Ambika, N. Keerthana, R. Srinivasan, “Realization of Silicon nanotube tunneling FET on junctionless structure Using Single and Multiple Gate workfunction”, Solid-State Electronics, Vol. 127, 2017, pp. 45–50.
  27. G Durga, and R Srinivasan, “SET Analysis of Silicon Nanotube FET”, Journal of Computational Electronics, Vol. 16, No. 2, 2017, pp. 307–315.
  28. G Durga, and R Srinivasan, “Silicon Nanotube SRAM and its SEU Reliability”, Superlattices and Microstructures, Vol. 106, 2017, pp. 129–138.
  29. Priscilla Scarlet, R Ambika and R Srinivasan, “Effect of Eccentricity on Junction and Junctionless-based Silicon Nanowire and Silicon Nanotube FETs”, Superlattices and Microstructures, Vol. 107, 2017, pp. 178–188.
  30. N. Vinodhkumar and R. Srinivasan, “Radiation performance of planar junctionless devices and junctionless SRAMs”, Journal of Computational Electronics, Vol. 15, No. 1, pp. 61–66, Mar 2016.
  31. R. Ambika, R. Srinivasan, “Performance Analysis of n-Type Junctionless Silicon Nanotube Field Effect Transistor”, Journal of Nanoelectronics and Optoelectronics, Vol. 11, 2016 (ASP Publisher).
  32. R. Ambika, R. Srinivasan, “Analysis of independent gate operation in Si nanotube FET and threshold prediction model using 3D numerical simulation”, Journal of Computational Electronics, Vol. 15, No. 1, pp. 61–66, Mar 2016.
  33. N. Keerthana, R. Ambika, R. Srinivasan, “Realization of Tunnel FET operation on Junctionless FET with Single Gate electrode Work function”, Journal of Nanoengineering and Nanomanufacturing, Vol. 6, 2016 (ASP Publisher).
  34. Maran Ponnambalam, Vinodhkumar, R Srinivasan, Premanand Chandramani, “Phase Displacement Study in MOSFET-based Ring VCOs Due to Heavy Ion Irradiation Using 3D TCAD and Circuit Simulations”, Microelectronics Reliability, Vol. 65, 2016, pp. 27–34.
  35. D. Suresh, K.K. Nagarajan, R. Srinivasan, “Impact of process variations on input impedance and mitigation using circuit technique in FinFET-based LNA”, Journal of Semiconductors, 2015, 36(4), pp. 045002–6.
  36. N. Vinodhkumar, Y.V. Bhuvaneshwari, K.K. Nagarajan, and R. Srinivasan, “Heavy-ion irradiation study in SOI-based and bulk-based junctionless FinFETs using 3D-TCAD simulation”, Microelectronics Reliability, Vol. 55, No. 12, 2015, pp. 2647–2653.
  37. K.K. Nagarajan and R. Srinivasan, “Investigation of Tunable Characteristics of Independently Driven Double Gate FinFETs in Analog/RF Domain Using TCAD Simulations”, Journal of Computational and Theoretical Nanoscience, Vol. 11, 2014, pp. 821–826.
  38. B. Lakshmi and R. Srinivasan, “Effect of Process Parameter Variation on ft in N-Type Junctionless FETs”, Journal of Computational Electronics, Vol. 12, 2013, pp. 454–459.
  39. B. Lakshmi and R. Srinivasan, “Performance Analysis of Dual Metal Gate Work function in junctionless FETs”, Journal of Computational and Theoretical Nanoscience, Vol. 10, 2013.
  40. K.K. Nagarajan and R. Srinivasan, “Process Variation Compensation in Independently Driven Double Gate FinFET-Based 10 GHz LNA using Mixed Mode TCAD Simulations”, European Journal of Scientific Research, Vol. 97, No. 2, 2013, pp. 263–271.
  41. V.N. Ramakrishnan and R. Srinivasan, “Effect of underlap and soft error performance in 30 nm FinFET-based 6T-SRAM cells with simultaneous and independent driven gates”, Journal of Computational Electronics, Vol. 12, 2013, pp. 469–475.
  42. V.N. Ramakrishnan and R. Srinivasan, “Soft Error Study in Double gated FinFET-Based SRAM Cells with Simultaneous and Independent Driven Gates”, Microelectronics Journal, Vol. 43, 2012, pp. 888–893.
  43. K.K. Nagarajan, N. Vinodhkumar and R. Srinivasan, “Optimization of Gate–Source/Drain Underlap on 30 nm Gate Length FinFET Based LNA Using TCAD Simulations”, WSEAS Transactions On Circuits And Systems, Vol. 11, No. 11, 2012, pp. 361–370.
  44. Vaithianathan, J. Raja, R. Srinivasan, “A 2–12 GHz Ultra Wide Band CMOS Low Noise Amplifier with High Gain and Linearity”, American Journal of Applied Sciences, Vol. 9, No. 8, 2012, pp. 1158–1165.
  45. Vaithianathan, J. Raja, R. Srinivasan, A. Naveen Bharadwaj, “A Low Power Fully Digital Transmitter for Ultra Wide Band Impulse Radio”, European Journal of Scientific Research, Vol. 74, No. 2, 2012, pp. 259–271.
  46. R. Srinivasan and Navakanta Bhat, “Optimisation of Gate-Drain/Source Overlap on Noise in 90 nm NMOSFETS for Low Noise Amplifier Performance”, Journal of Low Power Electronics, Vol. 4, No. 2, 2008, pp. 240–246.
  47. R. Srinivasan and Arup Ratan Saha, “Effect of STI, DSL and SMT on fT and noise-figure in 30 nm gate length NMOSFET”, International Journal of Electronics, Vol. 95, No. 10, 2008, pp. 1103–1109.

Projects executed in Semiconductor device simulation lab

FundAmountDurationTitle
DST21.8 lakhs2009-2012Process Variational study in Nano scale devices
DRDO30.47 lakhs2012-2015Soft error in novel devices based SRAM.
BRNS32 lakhs2020-2023Performance of SiGe Based RF Circuits

Sanction Order

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Past and present research Scholars of Semiconductor device simulation lab

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