August 9, 2024
Dr. Sree Hari Veeramachaneni – Assistant Professor
IT
Dr. Sree Hari Veeramachaneni
B.Tech, M.S, Ph.D.,
Assistant Professor
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INTERNATIONALCONFERENCES
Dr. Sree Hari Veeramachaneni, Assistant Professor – Grade-III, in the Department of Information Technology, SSN College of Engineering, Chennai, India. He completed his Bachelor’s degree in Electronics and Communications from Pondicherry University and his Master’s and PhD from IIIT Hyderabad. Prior to his association with SSN Chennai, he was working as an Associate Professor at GRIET Hyderabad.
He has 20 years of Academic and Research experience. His research interests include Computer Architecture, Image and Signal processing, Arithmetic Circuits for Approximate Computing, Hardware Security, Memory Design, Data Converters, Analog/Digital VLSI Design and Machine Learning, Deep Learning Applications. He is a reviewer of several IEEE/ACM/ Springer/Elsevier Journals. He is also IEEE and ACM Senior Member.
Publications
- Krishna, L.H. Sk, A. Rao, J.B. Veeramachaneni, S. Sk, N.M. “Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor” IEEE Embedded Systems Letters, 2024, 16(2), pp. 134–137
- Jonnalagadda, A.A., Kumar, U.A., Thotli, R., Veeramachaneni, S., Ahmed, S.E.“ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks” IEEE Access, 2024, 12, pp. 31036–31046
- Chandra, S.S., Kannan, R.J., Balaji, B.S., Veeramachaneni,, Noor Mahammad, S.” Efficient design and analysis of secure CMOS logic through logic encryption” Scientific Reports , 2023, 13(1), 1145
- Raghavendra Kumar, S., Balasubramanian, P., Reddy, R., Veeramachaneni, S., Sk, N.M. “Optimized Fault-Tolerant Adder Design Using Error Analysis” Journal of Circuits, Systems and Computers, 2023, 32(6), 2350091
- Krishna, L.H., Sk, A., Rao, J.B., Veeramachaneni, S., Sk, N.M.” Energy Efficient Approximate Multiplier Design with Lesser Error Rate using the Probability-based Approximate 4:2 Compressor” IEEE Embedded Systems Letters , 2023
- Jyothi, C., Saranya, K., Jammu, B.R., Veeramachaneni, S., Mahammad, S.N.,” A New Approximate 4-2 Compressor using Merged Sum and Carry” Journal of Electronic Testing: Theory and Applications (JETTA) t, 2022, 38(4), pp. 381–394
- Jammu, B.R., Guna Sekhar Sai Harsha, L., Bodasingi, N., Veeramachaneni, S., Sk, N.M.“Hardware efficient circuit for low error logarithmic converter” Journal of Computational Methods in Sciences and Engineering 2022, 22(2), pp. 511–527
- Harsha, L.G.S.S., Jammu, B.R., Bodasingi, N., Veeramachaneni, S., Sk, N.M.“A Low Error, Hardware Efficient Logarithmic Multiplier” Circuits, Systems, and Signal Processing , 2022, 41(1), pp. 485–513
- Guna Sekhar Sai Harsha, L., Jammu, B.R., Samoju, V.R., Veeramachaneni, S., Mohammad S, N. “A low-error, memory-based fast binary antilogarithmic converter” International Journal of Circuit Theory and Applications, 2021 https://doi.org/10.1002/cta.2981
Research Citations
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ORCID : 0000-0001-7744-4580 |
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Publons Researcher ID : AAT-7782-2021 |
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Scopus ID : 21835132600 |
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