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April 30, 2020

Dr. R. Srinivasan – Professor

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Dr. R. Srinivasan – Professor

IT

Dr. R. Srinivasan
Ph.D

Professor

Email: [email protected]

Extn: 403

34

INTERNATIONAL
JOURNALS

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INTERNATIONAL
CONFERENCES

R Srinivasan obtained his MS (By research) degree from the department of electrical engineering, Indian Institute of Technology, Madras in the year 1998. He received his Ph.D. degree from the department of electrical communication engineering, Indian Institute of Science, Bangalore in the year 2007.

He has experience both in industry as well as in academics. Since December 2007 he has been with the department of Information Technology, SSN College of Engineering.

His research interests include Image processing, anamorphic images, VLSI, nano-scale transistors, micro/nano-electronics and analog circuits.

He has established TCAD device simulation lab in the year 2009 which is located in one of the research labs of IT department.

He has supervised 6 full-time Ph.D. scholars, and 5 part-time Ph.D. scholars.

He has executed three projects worth Rs. 21.8 lakhs, 31 Lakhs, 30 lakhs sanctioned from DST, Govt. of India, DRDO, Govt. of India, and DAE, Govt. of India, (BRNS), respectively.

To his credit he has 45 journal papers.

  1. Sasikala PanneerSelvam, Sirish, TanuShyam Bhattacharjee, Premanand Venkatesh Chandramani, and Srinivasan Raj, “Impact of Process Variation on Leakage and Drive Currents of FED Structures Using Linear Regression and Random Forest Algorithms”, Silicon, Oct 2023 (Published online)
  2. Sasikala PanneerSelvam, Susanta Kumar Pal, Premanand Venkatesh Chandramani, Srinivasan Raj, “Single event performance of FED based SRAMs using numerical simulation”, Microelectronics Reliability, Volume 142, 2023, 114930, ISSN 0026-2714, (https://authors.elsevier.com/a/1gcwy5~JArUxo)
  3. G Durga, Susantakumar Pal, and R Srinivasan, “Reconfigurable FET based Tunable Ring Oscillator and its single event effect performance”, Journal of Circuits, Systems And Computers. (Accepted –https://www.worldscientific.com/doi/abs/10.1142/S0218126622400084)
  4. Suresh Durai, K C Chandinin Devi, Srinivasan Raj, and Anbarasu Manivannan, “Impact of Process Induced Ellipticity on the Reset Process of Cylindrical Phase Change Memory Devices”, Physica Scripta, Vol. 97, No. 12, 2022 (available online- https://iopscience.iop.org/article/10.1088/1402-4896/ac9dcd )
  5. L K Pavithra, R Srinivasan and T Sree Sharmila, Optimum Anamorphic Image Generation Using Image rotation and relative Entropy”, Multimedia Tools and Applications, Springer, 22nd April 2022 (Published Online)
  6. Scarlet, S.P., Vinodhkumar, N. & Srinivasan, R. “Performance enhancement of junctionless silicon nanotube FETs using gate and dielectric engineering”, Journal of computational electronics (Nov 2020),  https://doi.org/10.1007/s10825-020-01611-5
  7. Rajendran P, Nagarajan K K, and Srinivasan R, “Investigation of heavy ion strike on FinFET based low noise amplifier”, Semiconductor Science and Technology, Vol. 35, Nov. 2020.
  8. Suresh Durai, Srinivasan Raj, and Anbarasu Manivannan, “Impact of Thermal Boundary Resistance on the Performance and Scaling of Phase Change Memory Device”, IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 39, No. 9, Sep. 2020, pp. 1834-1840
  9. Nisha Justeena, and R Srinivasan, “Reconfigurable FET-Based SRAM and Its Single Event Upset Performance Analysis Using TCAD Simulations”, Microelectronics, Volume 101, July 2020.
  10. Nisha Justeena, and R Srinivasan, “Reconfigurable Silicon Nanotube FET Using Numerical Simulations”, Journal of computational electronics, Vol. 19, May 2020, pp. 966-974.
  11. Suresh Durai, Srinivasan Raj, and Anbarasu Manivannan, “Impact of Process-induced Variability on the Performance and Scaling of Ge2Sb2Te5 Phase-Change Memory Device”, Semiconductor Science and Technology, Vol. 35, No. 3, Feb. 2020.
  12. Suresh Durai, Srinivasan Raj, and Anbarasu Manivannan, “An extremely fast, energy-efficient RESET process in Ge2 Sb2 Te5 phase change memory device revealed by the choice of electrode materials and interface effects”, Semiconductor Science and Technology, Vol. 35, No. 1, Dec 2019
  13. Rajendran P, and Srinivasan R, “Single Event Radiation Performance Analysis of Junction and Junctionless FET-based Low Noise Amplifier”, Journal of computational electronics, Vol. 18, No. 3, July 2019, pp. 1162-1172.
  14. Rajendran P, and Srinivasan R, “‘Heavy ion impact on narrow band cascoded low noise amplifier’, Microelectronics Reliability, vol. 91, part – 1, pp. 31-37, 2018 (Impact factor: 1.236), (ISSN: 0026-2714).
  15. Scarlet, S, P and Srinivasan, R, “Optimization of nanometer bulk junctionless Trigate FET using gate and isolation dielectric engineering,” Material Science in Semiconductor processing, vol. 84, no. March, pp. 107–114, 2018.
  16. R.Ambika, R.Srinivasan, “Sensitivity of Silicon nanotube FETs to structural process parameters”, Journal of Nanoelectronics and Optoelectronics, Vol. 12, pp. 1–7, 2017 (ASP publisher)
  17. Priscilla Scarlet, and R Srinivasan, “Nanoscale Junctionless Device Using RingFet Structure on Bulk Silicon Substrate, International Journal of Electronic Letters, 2017.
  18. Priscilla Scarlet, and R Srinivasan, “Performance Optimisation of Junctionless FET in Nano regime using Segmented Channel- A 3D Numerical simulation study” Superlattices and Microstructures (Elsevier Publisher), Vol. 111, 2017.
  19. N. Vinodhkumar, and R.Srinivasan, “SET and SEU performance of Single, Double, Triple and Quadruple-Gate Junctionless FETs Using Numerical Simulations”, Microelectronics Journal (Elsevier Publisher), Vol. 67, Sep 2017 , 38-42.
  20. R.Ambika, N.Keerthana,R.Srinivasan ,”Realization of Silicon nanotube tunneling FET on junctionless structure Using Single and Multiple Gate workfunction “, Solid-State Electronics (Elsevier Publisher), Vol. 127 (2017) 45–50.
  21. G Durga, and R Srinivasan, “SET Analysis of Silicon Nanotube FET” Journal of computational electronics, Vol. 16, No. 2, 2017, 307-315.
  22. G Durga, and R Srinivasan, “Silicon Nanotube SRAM and its SEU Reliability” Superlattices and Microstructures (Elsevier Publisher),  Vol. 106, 2017, 129-138.
  23. Priscilla Scarlet, R Ambika and R Srinivasan, “Effect of Eccentricity on Junction and Junctionless-based Silicon Nanowire and Silicon Nanotube FETs” Superlattices and Microstructures (Elsevier Publisher), Vol. 107, 2017, 178-188.
  24. N. Vinodhkumar and R.Srinivasan, “Radiation performance of planar junctionless devices and junctionless SRAMs”, Journal of Computational Electronics, Vol.15, No.1, pp.61-66, March 2016.
  25. R.Ambika,R.Srinivasan,”Performance Analysis of n-Type Junctionless Silicon Nanotube Field Effect Transistor ”, Journal of Nanoelectronics and Optoelectronics,Vol. 11, pp. 1–7, 2016(ASP Publisher).
  26. R.Ambika,R.Srinivasan,”Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation”, Journal of Computational Electronics, Vol.15, No.1, pp.61-66, March 2016 (Springer)
  27. N.Keerthana,R.Ambika, R.Srinivasan,”Realization of Tunnel FET operation on Junctionless FET with Single Gate electrode Work function”,Journal of Nanoengineering and Nanomanufacturing , Vol. 6, pp. 1–4, 2016 (ASP Publisher).
  28. Maran Ponnambalam, Vinodthkumar, R Srinivasan, Premanand Chandramani,” Phase Displacement Study in MOSFET-based Ring VCOs Due to Heavy Ion Irradiation Using 3D TCAD and Circuit Simulations”, Microelectronics Reliability (Elsevier Publisher), Vol. 65, pp. 27-34, 2016.
  29. D. Suresh, K.K. Nagarajan, Dr. R. Srinivasan, “Impact of process variations on input impedance and mitigation using circuit technique in FinFET-based LNA”, Journal of Semiconductors, 2015,36(4), pp.045002-6.
  30. N. Vinodhkumar, Y.V.Bhuvaneshwari, K.K.Nagarajan and Dr.R.Srinivasan, “Heavy-ion irradiation study in SOI-based and bulk-based junctionless FinFETs using  3D-TCAD simulation”, Microelectronics Reliability (Elsevier Publisher), Vol.55, No.12, pp.2647-2653, December 2015.
  31. K.K.Nagarajan and R.Srinivasan, “Investigation of Tunable Characteristics of Independently Driven Double Gate FinFETs in Analog/RF Domain Using TCAD Simulations”, Journal of Computational and Theoretical Nanoscience, Vol.11,  pp.821-826, March   2014.
  32. B .Lakshmi and R.Srinivasan, “Effect of Process Parameter Variation on ft in N-Type Junctionless FETs”, Journal of Computational Electronics, Vol. 12, pp.454-459, April 2013.
  33. B.Lakshmi and R.Srinivasan, “Performace Analysis of Dual Metal Gate Work function in junctionless FETs”, Journal of Computational and Theoretical NanoScience,Vol.10,Jun2013.
  34. K.K.Nagarajan and R.Srinivasan, “Process Variation Compensation in Independently Driven Double Gate FinFET-Based 10 GHz LNA using Mixed Mode TCAD Simulations”, European Journal of Scientific Research, Vol.97,No.2,pp.263-271,February2013.
  35. V.N.Ramakrishnan and R.Srinivasan, “Effect of underlap and soft error performance in 30 nm FinFET-based 6T-SRAM cells with simultaneous and independent driven gates”, Journal of Computational Electronics, Vol. 12, pp.469-475,  May 2013.
  36. V.N.Ramakrishnan and R.Srinivasan, “Soft Error Study in Double gated FinFET-Based SRAM Cells with Simultaneous and Independent Driven Gates”,  Microelectronics Journal (Elsevier Publisher),Vol.43,pp.888-893,2012.
  37. K.K.Nagarajan, N.Vinodhkumar and R.Srinivasan, “Optimization of Gate – Source/Drain Underlap on 30 nm Gate Length FinFET Based LNA Using TCAD Simulations”, WSEAS Transactions On Circuits And Systems,Vol 11,No.11, pp.361-370,  November     2012.
  38. Vaithianathan, Dr. J. Raja, Dr. R. Srinivasan (2012), ‘A 2-12 GHz Ultra Wide Band CMOS Low Noise Amplifier with High Gain and Linearity’, American Journal of Applied Sciences, Vol. 9, No.8, pp.1158 – 1165.
  39. Vaithianathan, Dr. J. Raja, Dr. R. Srinivasan, A. Naveen Bharadwaj (2012), ‘A Low Power Fully Digital Transmitter for Ultra Wide Band Impulse Radio’, European Journal of Scientific Research, Vol.74 No.2, pp. 259-271, April 2012.
  40. R.Srinivasan and Navakanta Bhat, “Optimisation of Gate-Drain/Source Overlap on Noise in 90 nm NMOSFETS for Low Noise Amplifier Performance”, Journal of Low Power Electronics, Vol.4, No.2,pp.240-246,2008.
  41. R.Srinivasan and Arup Ratan Saha, “Effect of STI, DSL and SMT on fT and noise-figure in 30 nm gate length NMOSFET”, International Journal of Electronics,Vol.95,No.10, pp.1103-1109,2008.
  42. R Srinivasan and Navakanta Bhat, Scaling Characteristics of fNQS and ft in NMOSFETS with and without Supply Voltage Scaling, Journal of Indian Institute of Science, Vol 85, Aug 2005.
  43. R Srinivasan and Navakanta Bhat, Scaling Characteristics of fNQS and ft in NMOSFETS with Uniform and Non-uniform Channel Doping, International Journal of Electronics, Taylor and Francis Group, Vol 92, No 12, Dec 2005.
  44. R Srinivasan and Navakanta Bhat, Effect of Gate-Drain/Source Overlap on Noise in 90 nm NMOSFETS, Journal of Applied Physics, Vol 99, No 8, 2006.
  45. P R Vaya and R Srinivasan, Simulation Study of Znte/CdZnTe based quantum well lasers, Elsevier Material Science and Engineering B, Vol 57, 1, pp 71-75, Dec 1998.

Research Citations:

ORCID: 0000-0002-3362-3189

Publons ResearcherID: ABC-3858-2021

Scopus ID: 57213029026

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