Dr. R. Srinivasan

it_srinivasanProfessor
Dr. R. Srinivasan Ph.D

Email: srinivasanr@ssn.edu.in
Extn: 403

 

R Srinivasan obtained his MS (By research) degree from the department of electrical engineering, Indian Institute of Technology, Madras in the year 1998. His MS research thesis was on quantum well lasers and quantum well infrared photo-detectors. He received his Ph.D. degree from the department of electrical communication engineering, Indian Institute of Science, Bangalore in the year 2007. His dissertation was on RF CMOS device engineering and its performance analysis. To his credit he has 12 journal papers and 20 conference papers.

He has experience both in industry as well as in academics. After happy years in industry, he joined as a faculty member in the department of Information Technology, SSN College of Engineering in December 2007.

His research interests include VLSI, nano-scale transistors, micro/nano-electronics and analog circuits.

He executed a project of worth Rs. 21.8 lakhs sanctioned from department of science and technology, Govt. of India. The project is aimed to study the effect of process variational effects in nano-scale MOSFETs using TCAD simulations.

Currently he is running a project for DRDO of worth 31 Lakhs. The project is aimed to study the radiation effects on novel devices-based SRAM cells.

Journals and Conferences

Suresh D and R Srinivasan ” Impact of Process Variations on Input Impedance and Mitigation Using Circuit Technique in FinFET-Based LNA” Journal of Semiconductors (Accepted for publucation – received confirmation email on 24th Nov 2014)

K. K. Nagarajan, R. Srinivasan, “Performance analysis of dual metal gate work function in junctionless transistors”, Journal of Computational and Theoretical Nanoscience, Vol.11, pp. 821-826, 2014

B. Lakshmi, R. Srinivasan, “Performance analysis of dual metal gate work function in junctionless transistors”, Journal of Computational and Theoretical Nanoscience, Vol.10, pp. 1-5, 2013

V. N. Ramakrishnan, R. Srinivasan, “Effect of underlap and soft error performance in
30nm FinFET-based 6T-SRAM cells with simultaneous and independent driven gates”, Journal of Computational Electronics”, Vol. 12, Issue 3, pp. 469-475, May 2013

B. Lakshmi, R. Srinivasan, “Effect of Process Parameter Variation on ft in N-type Junctionless FETs”, Journal of Computational Electronics, Vol.12, pp. 454-459, 2013

V N Ramakrishnan and R Srinivasan, “Soft error study in double gated FinFET-based
SRAM cells with simultaneous and independent driven gates”, Elsevier-Microelectronics engineering Vol 43, No. 11, pp 888-893, Nov 2012

K K Nagarajan, N VinothKumar and R Srinivasan, “Optimization of Gate-Source/Drain Underlap on 30 nm Gate Length FinFET-based LNA Using TCAD Simulations”, WSEAS Transactions on circuits and systems Vol 11, No. 11, Nov 2012

R Srinivasan and Navakanta Bhat, Optimisation of Gate-Drain/Source Overlap on Noise in 90 nm NMOSFETS for Low Noise Amplifier Performance, Journal of Low Power Electronics, American Scientific Publishers, Vol 4, No 2, pp 240-246, 2008

R Srinivasan and Arup Ratan Saha, Effect of STI, DSL and SMT on fT and noise-figure in 30 nm gate length NMOSFET, International Journal of Electronics, Taylor and Francis Group, Vol 95, No 10, pp 1103-1109, 2008

R Srinivasan and Navakanta Bhat, Effect of Gate-Drain/Source Overlap on Noise in 90 nm NMOSFETS, Journal of Applied Physics, Vol 99, No 8, 2006

R Srinivasan and Navakanta Bhat, Scaling Characteristics of fNQS and ft in NMOSFETS with Uniform and Non-uniform Channel Doping, International Journal of Electronics, Taylor and Francis Group, Vol 92, No 12, Dec 2005

R Srinivasan and Navakanta Bhat, Scaling Characteristics of fNQS and ft in NMOSFETS with and with out Supply Voltage Scaling, Journal of Indian Institute of Science, Vol 85, Aug 2005

P R Vaya and R Srinivasan, Simulation Study of ZnTe/CdZnTe based quantum well lasers, Elsevier Material Science and Engineering B, Vol 57, 1, pp 71-75, Dec 1998